Throughout the prior art, metal gate integration has proven difficult to achieve in a conventional process flow for CMOS transistors. Most metal gate materials interact with the gate dielectric during the high temperature processing needed for source/drain (S/D) junction activation anneals. The need to keep the metal gate stack from receiving high temperature anneals has lead to the development of the “gate last” or “replacement gate” process for which the gate stack is fabricated last and remains below 500° C. during subsequent processing. Although the prior art replacement gate process increases the number of material choices for a metal gate, the process complexity and cost increases.
Co-assigned U.S. application Ser. No. 10/300,165, filed Nov. 20, 2002 describes an approach for forming a metal gate silicide in a conventional CMOS transistor processing flow in which the “replacement gate” process is not used. In this alternative approach, the number of added processing steps has been minimized therefore keeping the complexity to a minimum and cost down.
The avoidance of the “replacement gate” process is a big advantage. A second advantage to the approach described in the '165 application is the ability to deposit the silicide metal via standard physical vapor deposition. Since the metal is not being directly deposited on the gate dielectric in the '165 application, there is no need for chemical vapor deposition (CVD) or atomic layer deposition (ALD), which keeps the gate dielectric damage to a minimum by eliminating the use of a plasma. An additional advantage is the ease of passivation of the gate dielectric after silicide metal gate formation. Hydrogen readily diffuses through the silicide allowing passivation in a conventional furnace anneal process.
Forming the metal gate silicide in a conventional CMOS process flow can be accomplished with the addition of several steps. The following is an illustration of such a process flow: A nitride or oxide cap layer is typically needed on top of the gate polycrystalline Si (i.e., polySi) during the silicidation of the source/drain region. The oxide or nitride cap prevents silicidation of the gate polySi region during the source/drain silicidation. Besides the inclusion of the polySi cap, all other processing steps are conventional through the formation of the silicide contacts on the source/drain regions.
After silicide source/drain contact formation, a nitride/oxide bilayer is typically deposited on the CMOS structure and planarized so as to cover the source/drain silicide and the trench isolation regions. The planarization is typically performed utilizing a chemical mechanical polishing (CMP) process. CMP is performed such that the cap on the polySi gate stack is removed and the polySi is in contact with the planarized surface.
At this point, a conventional self-aligned silicide (i.e., salicide) process may be used to form the silicide metal gate. After this, the conventional CMOS integration flow is followed to form the multiple back end interconnect levels.
A disadvantage for the silicide metal gate process described above is that after CMP the polySi gate height (thickness) varies depending on the length of the gate. This variation comes about due to (1) the within-die, with-in wafer, wafer-to-wafer, and lot-to-lot non-uniformity during gate CMP, and (2) incoming topography between shallow trench isolation (STI) and silicon surface (active area) created during STI CMP and subsequent cleans.
Although STI CMP has been optimized to minimize STI-to-Si step height, such step height still exists and varies depending on the pattern density of the device. Any variation in such step height will be translated into gate height variation later on during the gate CMP. The gate CMP itself adds more non-uniformity and variation on gate height to features with different pattern densities. A combination of both can create up to 400 Å gate height variations within a given wafer. With such variation, when the silicide metal is deposited different phases of the silicide may form since in different gates there are differing amounts of polySi which can be consumed in the silicide formation. These different phases can lead to different workfunctions (hence transistor turn on voltages) and variations in resistance (device performance).
In view of the drawbacks mentioned above, there is a need for providing a new and improved CMOS silicide metal gate integration scheme that allows for the formation of a silicide metal gate on regions of polySi that have substantially the same height regardless of the gate dimensions.